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1 of 26 special features ? 16384 bits electrically programmable read only memory (eprom) communicates with the economy of one signal plus ground ? eprom partitioned into 64 256-bit pages for randomly accessing packetized data records ? each memory page can be permanently write protected to prevent tampering ? device is an ?add only? memory where additional data can be programmed into eprom without disturbing existing data ? architecture allows software to patch data by superseding an old page in favor of a newly programmed page ? reduces control, address, data, power, and programming signals to a single data pin ? 8-bit family code specifies DS1985 communications requirements to reader ? reads over a wide voltage range of 2.8v to 6.0v from -40c to +85c; programs at 11.5v to 12.0v from -40c to +85c f3 microcan f5 microcan common i button features ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike ? multidrop controller for microlan ? digital identification and information by momentary contact ? chip-based data carrier compactly stores information ? data can be accessed while affixed to object ? economically communicates to bus master with a single digita l signal at 16.3kbps ? standard 16mm diameter and 1-wire ? protocol ensure compatibility with i button ? family ? button shape is self-ali gning with cup-shaped probes ? durable stainless steel case engraved with registration number withstands harsh environments ? easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage ordering information part pin-package DS1985-f3+ f3 microcan DS1985-f5+ f5 microcan +denotes a lead(pb)-free/rohs-compliant package . examples of accessories ds9096p self-stick adhesive pad ds9101 multi-purpose clip ds9093ra mounting lock ring ds9093f snap-in fob ds9092 i button probe i button and 1-wire are registered trademark s of maxim integrated products, inc. 19-4892; rev 8/09 DS1985 16kb add-only i button
DS1985 2 of 26 i button description the DS1985 16kb add-only i button is a rugged read/write data carrier that identifies a nd stores relevant information about the product or person to which it is attached. this information can be accessed with minimal hardware, for example a single port pin of a microcontroller. the DS1985 consists of a factory- lasered registration number that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bit family code (0bh) plus 16kb of eprom th at is user-programmable. the power to program and read the DS1985 is derived entirely from the 1-wire communicat ion line. data is transferred serially via the 1-wire protocol that requires onl y a single data lead and a ground return. the entire device can be programmed and then write-protected if desired. a lternatively, the part may be programmed multiple times with new data being appended to, but not overwriting, existing data with each subsequent programming of the device. note: individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logica l 1. a provision is also included for indicating that a certain page or pages of data are no longer valid an d have been replaced with new or updated data that is now residing at an alternate page address. this page address redire ction allows software to patch data and enhance the flexibility of the device as a standa lone database. the 48-bit serial numb er that is factory-lasered into each DS1985 provides a guaranteed unique identity that allows for absolute traceability. the durable microcan package is highly resistant to harsh environments such as di rt, moisture, and shock. its compact button-shaped profile is self-aligning with cup-shaped receptacles, allowing the DS1985 to be used easily by human operators or automatic equipment. accesso ries permit the DS1985 to be mounted on printed circuit boards, plastic key fobs, photo-id badges, id bracelets, a nd many other objects. applications include work-in-progress tracking, elec tronic travelers, access control, storage of calibration constants, and debit tokens. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the DS1985. the DS1985 has three main data component s: 1) 64-bit lasered rom, 2) 16384-bits eprom data memory, and 3) 704-bits eprom status memory. the device deri ves its power for read operations entirely from the 1-wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and conti nues to operate off of this ?parasite? power source during the low times of the 1-wire line until it returns high to replenish the para site (capacitor) supply. during programming, 1-wire communication occurs at normal voltage levels and then is pulsed momentarily to the programming voltage to cause the selected eprom bits to be programmed. the 1-wire line must be able to provide 12 volts and 10 milliamperes to adequately program the eprom portions of the part. whenever programming voltage s are present on the 1-wire line a special high voltage detect circuit within the ds 1985 generates an internal logic sign al to indicate this condition. the hierarchical structure of the 1-wire protocol is shown in figure 2. th e bus master must first provide one of the four rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom. these commands operate on the 64-bit lasered rom portion of each device and can singulate a specific device if many are present on the 1-wire line as well as indicate to the bus master how many and what types of devices are present. th e protocol required for these rom function commands is described in figure 8. after a rom function command is successfully executed, the memory f unctions that operate on the eprom portions of the DS1985 become accessible and the bus master may issue any one of the figure 8. after a rom function command is successfully executed, the memory f unctions that operate on the eprom portions of the DS1985 become accessible and the bus master may issue any one of the five memory function commands speci fic to the DS1985 to read or progr am the various data fields. the protocol for these memory function co mmands is described in figure 5. a ll data is read and written least significant bit first.
DS1985 3 of 26 DS1985 block diagram figure 1 64-bit lasered rom each DS1985 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3.) the 64-bit rom and rom function cont rol section allow the DS1985 to operate as a 1-wire device and follow the 1-wire protocol detailed in the section ?1-wire bus system.? the memory functions required to read and program the eprom sections of th e DS1985 are not accessible until the rom function protocol has been satisfied. this pr otocol is described in the rom func tions flow chart (figure 8). the 1- wire bus master must first provid e one of four rom function commands : 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. after a rom f unction sequence has been su ccessfully executed, the bus master may then provide any one of the memory function commands specifi c to the DS1985 (figure 5). the 1-wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. additional information about the dallas semiconductor 1-wire cy clic redundancy check is available in the book of ds19xx i button standards. the shift register acting as the crc accumulator is in itialized to 0. then starting with the least significant bit of the family code, 1 bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th b it of the serial number has been entered, the shift register c ontains the crc value. shifting in th e 8 bits of crc should return the shift register to all 0s.
DS1985 4 of 26 hierarchical structure for 1-wire protocol figure 2 64-bit lasered rom figure 3 8-bit crc code 48- bit serial number 8-bit family code (0bh) msb lsb msb lsb msb lsb
DS1985 5 of 26 16384 bits eprom the memory map in figure 4 shows the 16384 bits ep rom section of the DS1985 which is configured as 64 pages of 32 bytes each. the 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. data is first written to the scratchpad and then ve rified by reading a 16-bit crc from the DS1985 that confirms proper receipt of th e data and address. if the buffer contents are correct, a programming voltage should be applied and th e byte of data will be written into the selected address in memory. this process ensures data inte grity when programming the memory. the details for reading and programming the 16384 bits eprom por tion of the DS1985 are given in the memory function commands section. eprom status bytes in addition to the 16384 bits of data memory the DS1985 provides 704 bits of status memory accessible with separate commands. the eprom status bytes can be read or programmed to indicate various condi tions to the software interrogating the DS1985. the first 8 bytes of the eprom status memory (addresses 000 to 007h) contain the write protect page bits that inhibit programming of th e corresponding page in the 16384-bit main memory area if the approp riate write protection bit is pr ogrammed. once a bit has been programmed in the write protect page section of the status memory, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be read. the next 8 bytes of the eprom st atus memory (addresses 020 to 027h) contain the write protect bits that inhibit altering the page address redirection byte corresponding to each page in the 16384-bit main memory area. the following 8 bytes within the eprom status memo ry (addresses 040 to 047h ) are reserved for use by the i button operating software tmex. their purpose is to indicate which memory pages are already in use. originally, all of these bits are unprogrammed, indicating that th e device does not store any data. as soon as data is written to any page of the device under control of tmex, the bit inside this bitmap corresponding to that page will be programmed to 0, marking this pa ge as used. these b its are application flags only and have no impact on th e internal logic of the DS1985. the next 64 bytes of the eprom status memory (a ddresses 100h to 13fh) c ontain the page address redirection bytes which indicate if one or more of the pages of da ta in the 16384 bits eprom section have been invalidated by software and redirected to the page addr ess contained in the appropriate redirection byte. the hardware of the DS1985 makes no decisions based on the contents of the page address redirection bytes. these additional bytes of status eprom allow for the redirection of an entire page to another page address, indicating that the data in the original page is no longer considered relevant or valid. with eprom technology, bits within a page can be changed from a logical 1 to a logical 0 by programming, but cannot be changed back. therefore, it is not possible to simply rewrite a page if the data requires changing or updating, but with space perm itting, an entire page of data can be redirected to another page within the DS1985 by writing the one?s comp lement of the new page address into the page address redirection byte that corresponds to the original (replaced) page. this architecture allows the user?s software to ma ke a ?data patch? to the eprom by indicating that a particular page or pages should be replaced with those indicated in th e page address redirection bytes. to leave an authentic audit trail of data patches, it is recommended to also program the write protect bit of the page address redirection by te, after the page redirection is programmed. without this protection, it is still possible to modify the page address redi rection byte, making it point to a different memory page than the true one.
DS1985 6 of 26 if a page address redirection byte has a ffh value, th e data in the main memory that corresponds to that page is valid. if a page address redirection byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the one?s complement of the page address indicated by the hex value stored in the associated page address redirection byte. a value of fdh in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. the details for readi ng and programming the ep rom status memory portion of the DS1985 are given in the memory function commands section. ds 1985 memory map figure 4 redirection bytes bit map of used pages write-protect bits redirection bytes write-protect bits data memory status memory map bit 0 of address 000h= write protect of page 0, etc. address 100h=page address redirection byte for page 0, etc . 8-bit scratchpad 88 bytes status memory
DS1985 7 of 26 the status memory address range of the DS1985 ex tends from 000 to 13fh. the memory locations 008h to 01fh, 028h to 03fh, 048h to 0ffh and 140h to 7ffh are physic ally not implemented. reading these locations will usually result in ffh byt es. attempts to write to these locations will be ignored. if the bus master sends a st arting address higher than 7ffh, the five most significant address bits are set to 0s by the internal circuitry of the chi p. this will result in a mismatch between the crc calculated by the DS1985 and the crc calculated by the bus master, indicat ing an error condition. memory function commands the ?memory function flow chart? (figure 5) de scribes the protocols ne cessary for accessing the various data fields within the DS1985. the memory function control section, 8-bit scratchpad, and the program voltage detect circuit combine to interpre t the commands issued by the bus master and create the correct control signals within the device. a 3-byte protocol is issued by the bus master. it is comprised of a command byte to determine the type of operation and two address bytes to determine the specific starting byte location within a data field. the comma nd byte indicates if the device is to be read or written. writing data involves not only issuing the correct command sequence but also providing a 12v programming voltage at the appropriate times. to execu te a write sequence, a byte of data is first loaded into the scratchpad and then programmed into the sele cted address. write sequences always occur a byte at a time. to execute a read sequen ce, the starting address is issued by the bus master and data is read from the part beginning at that initial location and con tinuing to the end of the se lected data field or until a reset sequence is i ssued. all bits tr ansferred to the DS1985 and received back by the bus master are sent least significant bit first. read memory [f0h] the read memory command is used to read data fr om the 16384-bits eprom data field. the bus master follows the command byte with a two byte addre ss (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. with ev ery subsequent read data time slot the bus master receives data from the DS1985 starting at the initial address and continuing until the end of the 16384-bits data field is reached or until a reset pulse is issue d. if reading occurs through the end of memory space, the bus master may issue sixteen additional read time slots and the DS1985 will respond with a 16-bit crc of the command, address bytes and all data bytes r ead from the initial starting byte through the last byte of memory. this crc is the result of clearing the crc generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed memory location and continuing through to th e last byte of the eprom data memory. after the crc is received by the bus master, any subsequent read time slots will appear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse pr ior to reaching the end of memory will not have the 16-bit crc available. typically a 16-bit crc would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see book of ds19xx ibutton standards, ch apter 7 for the recommended file st ructure to be used with the 1- wire environment.) if crc values are imbedded within the data, a reset pulse may be issued at the end of memory space during a read memory command.
DS1985 8 of 26 read status [aah] the read status command is used to read data fr om the eprom status data field. the bus master follows the command byte with a 2-byte address (ta1 =(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. with every subsequent read data time slot the bus master receives data from the DS1985 starting at the supplied address and c ontinuing until the end of an 8-byte page of the eprom status data field is reached. at that poi nt the bus master will receive a 16-bit crc of the command byte, address bytes and status data bytes. this crc is computed by the DS1985 and read back by the bus master to check if the command word, starti ng address and data were received correctly. if the crc read by the bus master is incorrect, a reset puls e must be issued and the entire sequence must be repeated. note that the initial pass through the read status flow chart will generate a 16-bit crc value that is the result of clearing the crc generator and then shif ting in the command byte followed by the two address bytes, and finally the data bytes beginning at the first addressed me mory location and continuing through to the last byte of the addressed eprom status data pa ge. the last byte of a status data page always has an ending address of xx7 or xxfh. s ubsequent passes through the read st atus flow chart will generate a 16-bit crc that is the result of clear ing the crc generator and then shifti ng in the new data bytes starting at the first byte of the next page of the eprom status data field. this feature is provided since the eprom status information may change over time making it impossible to program the data once and include an accompanyi ng crc that will always be valid. therefore, the read status command supplies a 16-b it crc that is based on and always is consistent with the current data stored in the epro m status data field. after the 16-bit crc of the last eprom status data pa ge is read, the bus master will receive logical 1s from the DS1985 until a reset pulse is issued. the r ead status command sequence can be ended at any point by issuing a reset pulse.
DS1985 9 of 26 memory function flow chart figure 5
DS1985 10 of 26 memory function flow chart (cont?d) figure 5
DS1985 11 of 26 memory function flow chart (cont?d) figure 5
DS1985 12 of 26 extended read memory [a5h] the extended read memory command supports page redirection when reading data from the 16384-bit eprom data field. one major difference between the extended read memory and the basic read memory command is that the bus master receives the redirection byte first before investing time in reading data from the addressed memory location. this allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to terminate and restart the reading process at the redirected page address. a non-redirected page is identified by a redirection byte with a value of ffh (see description of eprom status bytes). if the redirection byte is different than this, the master has to complement it to obtain the new page number . multiplying the page number by 32 (20h) results in the new address the master has to send to the DS1985 to read the updated data replacing the old data. there is no logical limitation in the nu mber of redirections of any page . the only limit is the number of available memory pages within the DS1985. in addition to page redirection, the extended r ead memory command also supports ?bit-oriented? applications where the user cannot st ore a 16-bit crc with the data itself . with bit-oriented applications the eprom information may change over time with in a page boundary making it impossible to include an accompanying crc that will always be valid. therefore, the extended read memory command concludes each page with the DS1985 generating and supplying a 16-bit crc that is based on and therefore always consistent with th e current data stored in each page of the 16384-bit eprom data field. after having sent the command code of the extende d read memory command, the bus master follows the command byte with a 2-byte address (ta1=(t7:t 0), ta2=(t15:t8)) that indicates a starting byte location within the data field. by se nding eight read data time slots, the master receives the redirection byte associated with the page given by the starting address. with the next sixteen read data time slots, the bus master receives a 16-bit crc of the command byt e, address bytes and the redirection byte. this crc is computed by the DS1985 and read back by the bus master to check if the command word, starting address and redirection byte were received correctly. if the crc read by the bus master is incorrect, a reset pulse must be issued and the en tire sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the DS1985 starting at the initial address and continuing until the end of a 32-byte page is reached. at that point the bus master will send 16 additional read time slots and receive a 16-bit crc that is the result of shifting in to the crc generator all of the data bytes from the initial starting byte to the last byte of the current page. with the next 24 read data time slots the master will receive the redirection byte of the next page followed by a 16-bit crc of the redirection byte. afte r this, data is again read from the 16384-bit eprom data field starting at the be ginning of the new page. this sequen ce will continue until the final page and its accompanying crc ar e read by the bus master. the extended read memory command provides a 16-bit crc at two locations within the transaction flow chart: 1) after the redirection byte and 2) at the end of each memory page. the crc at the end of the memory page is always the result of cleari ng the crc generator and shifting in the data bytes beginning at the first addressed memory location of the eprom data page until the last byte of this page. the crc received by the bus master directly follo wing the redirection byte, is calculated in two different ways. with the initial pass through the exte nded read memory flow chart the 16-bit crc value is the result of shifting the command byte into the cleared crc generator, followed by the two address bytes and the redirection byte. s ubsequent passes through the extended read memory flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the redirection byte only.
DS1985 13 of 26 write memory [0fh] the write memory command is used to program th e 16384?bit eprom data field. the bus master will follow the command byte with a two byte starting a ddress (ta1=(t7:t0), ta2=(t15:t8)) and a byte of data (d7:d0). a 16-bit crc of the command byte, address bytes, and data byte is computed by the DS1985 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. the highest starting addre ss within the DS1985 is 07ffh. if the bus master sends a starting address higher than this, the five mo st significant address bits are set to 0 by the internal circuitry of the chip. this will result in a mismatch between the crc calcula ted by the DS1985 and the crc calculated by the bus master, indicating an error condition. if the crc read by the bus master is incorrect, a reset pulse must be i ssued and the entir e sequence must be repeated. if the crc received by the bus master is correct, a programmi ng pulse (12 volts on the 1- wire bus for 480 ? s) is issued by the bus master. prior to programming, the entire unprogrammed 16384- bit eprom data field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the 16384-bit eprom will be programmed to a logical 0 after the programming pulse has been applied at that byte location. after the 480 ? s programming pulse is applied a nd the data line returns to the idle level, the bus master issues eight read time slots to verify that th e appropriate bits have been programmed. the DS1985 responds with the data from the selected eprom address sent least significant bit first. this byte contains the logical and of all bytes written to this eprom data addre ss. if the eprom data byte contains 1s in bit positions where the byte issued by the master c ontained 0s, a reset pulse should be issued and the current byte address should be programmed again. if the DS1985 eprom data byte contains 0s in the same bit positions as the data byte, the program ming was successful and the DS1985 will automatically increment its address counter to se lect the next byte in the 16384-bi t eprom data field. the new 2-byte address will also be loaded into the 16-bit crc gene rator as a starting value. the bus master will issue the next byte of data us ing eight write time slots. as the DS1985 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the current address and the result is a 16-bit crc of the new data byte and the new address. after supplying the data byte, the bus master will read this 16-bit crc from the DS1985 with 16 read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued and the write memory command sequence must be restarted. if the crc is correct, th e bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write memory flow chart will generate a 16-bit crc value that is the result of shifting the command byte into the crc generator, followed by the two address bytes, and finally the data byte. subsequent passes through the write memory flow chart due to the DS1985 automatically incrementing its address counter will gene rate a 16-bit crc that is the result of loading (not shifting) the new (incremented) addr ess into the crc generator and then shifting in the new data byte.
DS1985 14 of 26 for both of these cases, the decision to continue (to apply a program pulse to the DS1985) is made entirely by the bus master, since th e DS1985 will not be able to determin e if the 16-bit crc calculated by the bus master agrees with the 16-bit crc calculate d by the DS1985. if an incorrect crc is ignored and a program pulse is applied by the bus master, in correct programming could occur within the DS1985. also note that the DS1985 will always increment its internal address coun ter after the recei pt of the eight read time slots used to confirm th e programming of the selected eprom byte. the decision to continue is again made entirely by the bus master, therefore if the eprom data byte does not match the supplied data byte but the master conti nues with the write memory command, incorrect programming could occur within the DS1985. the write memory command sequen ce can be ended at any point by issuing a reset pulse. to save time when writing more than one consecutive byte of the DS1985?s data memory it is possible to omit reading the 16-bit crc, which allows verification of data and address before the data is copied to the eprom memory. this saves 16 time slots or 976 ? s for every byte to be programmed. this speed- programming mode is accessed with the command code f3h instead of 0fh. it follows basically the same flow chart as the write memory command, but skips sending the crc i mmediately preceding the program pulse. this command should only be used if the electrical contact betw een bus master and the DS1985 is firm since a poor contact may result in corrupted data inside the eprom memory. write status [55h] the write status command is used to program the ep rom status data field. th e bus master will follow the command byte with a 2-byte star ting address (ta1=(t7:t0), ta2=(t15: t8)) and a byte of status data (d7:d0). a 16-bit crc of the command byte, addre ss bytes, and data byte is computed by the DS1985 and read back by the bus master to confirm that the correct command word, st arting address, and data byte were received. if the crc read by the bus master is incorrect, a reset pulse must be i ssued and the entir e sequence must be repeated. if the crc received by the bus master is correct, a programmi ng pulse (12 volts on the 1- wire bus for 480 ? s) is issued by the bus master . prior to programming, the ep rom status data field will appear as logical 1s. for each bit in the data byte provi ded by the bus master that is set to a logical 0, the corresponding bit in the selected byt e of the eprom status data field will be programmed to a logical 0 after the programming pulse has been applied at that byte location. after the 480 ? s programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that th e appropriate bits have been programmed. the DS1985 responds with the data from the selected eprom status address sent least signifi cant bit first. this byte contains the logical and of all bytes written to this eprom status byte address. if the eprom status byte contains 1s in bit positions where the byte issued by the master contained 0s, a reset pulse should be issued and the current byte address should be programmed again. if the DS1985 eprom status byte contains 0s in the same bit posit ions as the data byte, the programming was successful and the DS1985 will automatically increment its address counter to se lect the next byte in the eprom status data field. the new two-byte address will also be loaded into the 16-bit crc genera tor as a starting value. the bus master will issue the next byte of data using eight write time slots.
DS1985 15 of 26 as the DS1985 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the current address, and the result is a 16-bit crc of the new data byte and the new address. after supplying the data byte, the bus master will read this 16-bit crc from the DS1985 with 16 read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued a nd the write status command sequence must be restarted. if the crc is correct, the bus ma ster will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write status fl ow chart will generate a 16-bit crc value that is the result of shifting the command byte into the crc gene rator, followed by the 2 ad dress bytes, and finally the data byte. subsequent passes through the write status flow chart due to the DS1985 automatically incrementing its address counter will generate a 16-bit crc that is the re sult of loading ( not shifting) the new (incremented) address into the crc genera tor and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the DS1985) is made entirely by the bus master, since th e DS1985 will not be able to determin e if the 16-bit crc calculated by the bus master agrees with the 16-bit crc calculate d by the DS1985. if an incorrect crc is ignored and a program pulse is applied by the bus master, in correct programming could occur within the DS1985. also note that the DS1985 will always increment its internal address coun ter after the recei pt of the eight read time slots used to confirm th e programming of the selected eprom byte. the decision to continue is again made entirely by the bus master, therefore if the eprom data byte does not match the supplied data byte but the master continue s with the write status command, in correct programming could occur within the DS1985. the write status command sequen ce can be ended at any point by issuing a reset pulse. to save time when writing more than one consecutiv e byte of the DS1985s status memory it is possible to omit reading the 16-bit crc which allo ws verification of data and addre ss before the data is copied to the eprom memory. this saves 16 time slots or 976 ? s for every byte to be programmed. this speed- programming mode is accessed with the command c ode f5h instead of 55h. it follows basically the same flow chart as the write status command, but skips sending the crc immediately preceding the program pulse. this command should only be used if the electrical contact betw een bus master and the DS1985 is firm since a poor contact may result in co rrupted data inside th e eprom status memory. 1-wire bus system the 1-wire bus is a system that has a single bus ma ster and one or more slav es. in all instances, the DS1985 is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transacti on sequence, and 1-wire signaling (signal type and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling e dge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx i button standards. hardware configuration the 1-wire bus has only a si ngle line by definition; it is important that each devi ce on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have an open drain connection or 3- state outputs. the DS1985 is an open dr ain part with an internal circuit equivalent to that shown in figure 6. the bus master can be the same equivalent ci rcuit. if a bidirectional pin is not available, sepa rate output and input pins can be tied together.
DS1985 16 of 26 the bus master requires a pullup resistor at the ma ster end of the bus, with the bus master circuit equivalent to the one shown in figures 7a a nd 7b. the value of the pullup resistor should be approximately 5 k ? for short line lengths. a multidrop bus consists of a 1-wire bus with multip le slaves attached. the 1-wire bus has a maximum data rate of 16.3kbps. if the bus master is also re quired to perform programmi ng of the eprom portions of the DS1985, a programming supply cap able of delivering up to 10 mi lliamps at 12 volts for 480 ? s is required. the idle state for the 1-wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transac tion is to resume. if this does not occur and the bus is left low for more than 120 ? s, one or more of the device s on the bus may be reset. transaction sequence the sequence for accessing the DS1985 via the 1-wire port is as follows: ? ? initialization ? ? rom function command ? ? memory function command ? ? read/write memory/status initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus mast er followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus ma ster know that the DS1985 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 8): read rom [33h] this command allows the bus master to read the DS1985?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can be used onl y if there is a single DS1985 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result).
DS1985 17 of 26 DS1985 equivalent circuit figure 6 bus master circuit figure 7 to data connection of ds2505 capacitor added to reduce coupling on data line due to programming signal switching vp0300l or vp0106n3 or bss110
DS1985 18 of 26 rom functions flow chart figure 8 (see figure 5)
DS1985 19 of 26 match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific DS1985 on a multidrop bus. only the DS1985 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function co mmand. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit rom c ode. if more than one slave is present on the bus and a read command is issued following the skip ro m command, data collision will occur on the bus as multiple slaves transmit simultaneously (open dr ain pulldowns will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus mast er might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64 -bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, thr ee-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be iden tified by additional passes. see chapter 5 of the book of ds19xx ibutton standards for a comprehensive discussion of a rom sear ch, including an actual example. 1-wire signaling the DS1985 requires strict protocols to ensure data integrity. the prot ocol consists of five types of signaling on one line: reset sequen ce with reset pulse and presence pu lse, write 0, write 1, read data and program pulse. all these signals except pr esence pulse are initiated by the bus master. the initialization sequence required to begin any comm unication with the DS1985 is shown in figure 9. a reset pulse followed by a presence pulse indicate s the DS1985 is ready to accept a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 ? s). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on th e data pin, the DS1985 waits (t pdh , 15-60 ? s) and then transmits the presence pulse (t pdl , 60-240 ? s). read/write time slots the definitions of write and read time slots are illu strated in figure 10. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the DS1985 to the master by triggering a delay circuit in th e DS1985. during write time slots, the delay circuit determines when the DS1985 will sample the data line. for a read data time sl ot, if a ? 0 ? is to be transmitted, the delay circuit determines how long the DS1985 will hold the data line low overriding the 1 generated by the master. if the data bit is a ?1?, the i button will leave the read data time slot unchanged. program pulse to copy data from the 8-bit scratchpad to the ep rom data or status memory, a program pulse of 12 volts is applied to the data line after the bus master ha s confirmed that the crc for the current byte is correct. during programming, the bus master controls th e transition from a state where the data line is idling high via the pullup resistor to a state where the data line is actively driven to a programming voltage of 12 volts providing a minimum of 10 ma of current to the DS1985. this programming voltage
DS1985 20 of 26 (figure 11) should be applied for 480 ? s, after which the bus master returns the data line to an idle high state controlled by the pullup resistor. note that due to the high voltage programming requirements for any 1-wire eprom device, it is not possible to multidrop non-eprom based 1-wire devices with the DS1985 during programming. an internal diode with in the non-eprom based 1-wire devices will attempt to clamp the data line at approximately 8 volts and could potentially damage these devices. initialization procedure ?r eset and prese nce pulses? figure 9 480 ? s ? t rstl < ? * 480 ? s ? t rsth < ? (includes recovery time) 15 ? s ? t pdh < 60 ? s 60 ? s ? t pdl < 240 ? s ? in order not to mask interrupt signali ng by other devices on the 1-wire bus, t rstl + t r should always be less than 960 ? s. read/write timing diagram figure 10 write-1 time slot 60 ? s ? t slot < 120 ? s 1 ? s ? t low1 < 15 ? s 1 ? s ? t rec < ? resistor master resistor master DS1985
DS1985 21 of 26 read/write timing diagram (cont?d) figure 10 write-0 time slot 60 ? s ? t low0 < t slot < 120 ? s 1 ? s ? t rec < ? read-data time slot 60 ? s ? t slot < 120 ? s 1 ? s ? t lowr < 15 ? s 0 ? t release < 45 ? s 1 ? s ? t rec < ? t rdv = 15 ? s t su < 1 ? s resistor master DS1985
DS1985 22 of 26 program pulse timing diagram figure 11 crc generation with the DS1985 there are two different types of crcs (cyclic redundancy checks). one crc is an 8- bit type and is stored in the most significant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of th e 64-bit rom and compare it to the value stored within the DS1985 to determine if the rom data has been received error-f ree by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (non-inverted) form when reading the rom of the ds19 85. it is computed once at the f actory and lasered into the rom. the other crc is a 16-bit type, generated according to the standardized crc16-polynomial function x 16 + x 15 + x 2 + 1. this crc is used to safe guard user-defined ep rom data when reading data memory or status memory. it is the same type of crc as is used w ith nv ram based i buttons to safeguard data packets of the i button file structure. in contrast to the 8- bit crc, the 16-bit crc is always returned in the complemented (inverted) form. a crc-generator in side the DS1985 chip (figure 12) will calculate a new 16-bit crc at every situation shown in the command flow chart of figure 5. the DS1985 provides this crc-value to the bus master to validate the transfer of command, address, and data to and from the bus master. when reading th e data memory of the DS1985 with the read memory command, the 16-bit crc is only transmitted as the end of the memory is reached. this crc is generated by clearing the crc gene rator, shifting in the command, low address, high address and every data byte starting at the first addressed memory lo cation and continuing until the end of the implemented data memory is reached. when reading the status memory with the read st atus command, the 16-bit crc is transmitted when the end of each 8-byte page of the status memory is reached. at the initia l pass through the read status flow chart the 16-bit crc will be generated by clearing th e crc generator, shifting in the command byte, low address, high address and the data bytes beginning at the first addressed memory location and continuing until the last byte of the addressed eprom status da ta page is reached. subsequent passes through the read status flow chart will genera te a 16-bit crc that is the resu lt of clearing the crc generator and then shifting in the new data bytes starting at the fi rst byte of the next page of the eprom status data field and continuing until the last byte of the page is reached. line type legend: bus master active high (12v @ 10 ma) resistor p ullu p
DS1985 23 of 26 when reading the data memory of the DS1985 with the extended read memory command, there are two situations where a 16-bit crc is transmitted. one 16-b it crc follows each redirection byte, another 16- bit crc is received after the last byte of a memory data page is read. the crc at the end of the memory page is always the result of clear ing the crc generator and shifting in th e data bytes beginning at the first addressed memory location of the eprom data page un til the last byte of this page. with the initial pass through the extended read memory flow chart the 16-bit crc value is the re sult of shifting the command byte into the cleared crc gene rator, followed by the 2 address bytes and the redirection byte. subsequent passes through the exte nded read memory flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the redi rection byte only. when writing to the DS1985 (either data memory or st atus memory), the bus master receives a 16-bit crc to verify the correctness of the data transfer before applying the programming pulse. with the initial pass through the write memory/status flow chart th e 16-bit crc will be generated by clearing the crc generator, shifting in the comma nd, address low, address high and the data byte. subsequent passes through the write memory/status flow chart due to the DS1985 automatically incrementing its address counter will generate an 16-bit crc th at is the result of loading (not shifting) the new (incremented) address into the crc generator and then shifting in the new data byte. the comparison of crc values and decision to continue with an operation are de termined entirely by the bus master. there is no circuitry on the DS1985 that prevents a command sequence from proceeding if the crc stored in or calculated by the DS1985 does not match the value generate d by the bus master. for more details on generating crc values including example implementations in both hardware and software, see the book of ds19xx i button standards. crc-16 hardware descript ion and polynomial figure 12 polynomial = x 16 + x 15 + x 2 + 1
DS1985 24 of 26 absolute maxi mum ratings* voltage on any pin relative to ground -0.5v to +12.0v operating temperature -40c to +85c storage temperature -55c to +125c ? this is a stress rating only and functional operati on of the device at these or any other conditions outside those indicated in the ope ration sections of th is specification is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1,6 logic 0 v il -0.3 +0.8 v 1,10 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1,2 input load current i l 5 ? a 3 operating charge q op 30 nc 7,8 programming voltage @ 10 ma v pp 11.5 12.0 v capacitance (t a = 25 ? c) parameter symbol min typ max units notes data (1-wire) c in/out 800 pf 9 ac electrical characteristics (v pup =2.8v to 6.0v; -40 ? c to +85 ? c) parameter symbol min typ max units notes time slot t slot 60 120 ? s write-1 low time t low1 1 15 ? s write-0 low time t low0 60 120 ? s read data valid t rdv exactly 15 ? s release time t release 0 15 45 ? s read data setup t su 1 ? s 5 recovery time t rec 1 ? s reset time high t rsth 480 ? s 4 reset time low t rstl 480 ? s presence detect high t pdhigh 15 60 ? s presence detect low t pdlow 60 240 ? s delay to program t dp 5 ? s delay to verify t dv 5 ? s program pulse width t pp 480 ? s program voltage rise time t rp 0.5 5.0 ? s program voltage fall time t fp 0.5 5.0 ? s
DS1985 25 of 26 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. if v pup is lower than 3.0v the firs t byte read (any read command) may not reproduce the correct memory contents. therefore, under low voltage conditions, it is recommended to set either the most significant bit or all five most significa nt bits of ta2 to 1. internal circuitry of the chip will force these five bits back to 0 before they are shifted in the address counter and crc generator. 3. input load is to ground. 4. an additional reset or communication sequence ca nnot begin until the rese t high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 ? s of this falling edge a nd will remain valid for 14 ? s minimum. (15 ? s total from falling edge on 1-wire bus.) 6. v ih is a function of the external pullup resistor and v pup . 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5k ? pullup to v cc and a maximum time slot of 120 ? s. 9. capacitance on the data pin could be 800 pf when power is firs t applied. if a 5k ? resistor is used to pull up the data line to v cc , 5 ? s after power has been applied the parasite capacitance will not affect normal communications. 10. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse.
DS1985 maxim cannot assume responsibili ty for use of any circuitry other than circuitry entirely embodied in a maxim product. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim pr oduct. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. 26 of 26 revision history revision date description pages changed 071508 updated the f3 microcan and f5 microcan face brands with the latest per pcn h020201. 1 8/09 added the + sign to the part numbers in the ordering information table, indicating lead(pb)-fre e/rohs-compliant packages. 1 removed the ul#913 bullet from the common i button features section. 1

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